CrashDSL
Type members
Inherited types
Libretto arrow, also called a ''component'' or a ''linear function''.
┏━━━━━━━━━━┓
┞───┐ ┞───┐
╎ A │ ╎ B │
┟───┘ ┟───┘
┗━━━━━━━━━━┛
In A -⚬ B, we say that the ''in-port'' is of type A and the ''out-port'' is of type B.
Note that the distinction between the in-port and the out-port is only formal. Information or resources
may flow in and out through both the in-port and the out-port.
"Linear" means that each input is ''consumed'' exactly once, in particular, it cannot be ignored or used twice.
- Inherited from
- CoreDSL
Choice between A and B.
The consumer chooses whether to get A or B (but can get only one of them).
The producer has to be ready to provide either of them.
- Inherited from
- CoreDSL
Either A or B. Analogous to scala.Either.
Whether it is going to be A or B is decided by the producer.
The consumer has to be ready to handle either of the two cases.
- Inherited from
- CoreDSL
Value members
Methods
Crashes the program. Use only for irrecoverable errors.
Recoverable errors should be expressed in function signature and handled appropriately.
Done in the input is the trigger to crash. Done in the output is an obligation to propagate the crash. A in the input allows to consume any unhandled resources. B in the output allows to fulfill any obligation to produce resources.
Inherited methods
Races the two Done signals and - produces left if the first signal wins, in which case it returns the second signal that still has to be awaited; - produces right if the second signal wins, in which case it returns the first signal that still has to be awaited. It is biased to the left: if both signals have arrived by the time of inquiry, returns left.
- Inherited from
- CoreDSL
Races two Need signals, i.e. signals traveling in the negative direction (i.e. opposite the -⚬ arrow).
Based on which Need signal from the out-port wins the race,
selects one of the two Need signals from the in-port:
- If the first signal from the out-port wins the race, selects the left signal from the in-port
and pipes to it the remaining (i.e. the right) signal from the out-port.
- If the second signal from the out-port wins the race, selects the right signal from the in-port
and pipes to it the reamining (i.e. the left) signal from the out-port.
It is biased to the left: if both signals from the out-port have arrived by the time of inquiry,
selects the left signal from the in-port.
- Inherited from
- CoreDSL
Signals (in the negative direction) when it is known which side of the choice (A |&| B) has been chosen.
- Inherited from
- CoreDSL
Signals when it is decided whether A |+| B actually contains the left side or the right side.
- Inherited from
- CoreDSL